If you have tried to procure Nvidia Blackwell GPUs for your infrastructure in 2026, you already know the answer to “how long does it take?” is measured in quarters, not weeks. Delivery windows have slipped into Q1 2027. And yet TSMC is pouring billions into new production lines. So why is the hardware still scarce?
Here is the thing: chips are being made. The problem is finishing a shippable AI accelerator requires a second, completely separate manufacturing step that almost nobody covers. It is called advanced packaging. Specifically, CoWoS — Chip-on-Wafer-on-Substrate — and TSMC controls approximately 90% of the capacity needed to do it at AI-chip scale.
TSMC CEO C.C. Wei has confirmed that CoWoS is “sold out through 2025 and into 2026.” That is not a temporary blip. It is a structural constraint — and a completely different problem from wafer fabrication. The TSMC Arizona expansion that dominates semiconductor headlines addresses fabrication, not packaging. Arizona packaging is not on the cards until 2029.
This is part of the AI memory crunch — the cluster of supply chain bottlenecks shaping every AI infrastructure decision in 2026 and 2027. By the end of this article, you will understand what CoWoS is, why it cannot be quickly replicated, and what it means for enterprise GPU availability over the next 18 months.
What Is CoWoS Packaging and Why Does It Matter for AI Chips?
CoWoS places a GPU logic die and HBM memory stacks side-by-side on a silicon interposer inside a single package. That tight physical integration enables the high-density interconnects AI accelerators need to feed data between compute and memory. Without CoWoS, a fabricated GPU die and an HBM stack are two separate components sitting on a shelf. CoWoS is what turns them into a functional AI accelerator.
The key ingredient is the silicon interposer — a thin silicon die that acts as a high-density wiring layer connecting the GPU and HBM stacks via thousands of short electrical paths. Conventional PCB substrates simply cannot achieve the connection density AI workloads require.
Think of it this way: wafer fabrication produces the processing cores. CoWoS is the high-speed interconnect fabric that lets those cores actually talk to memory. Skip CoWoS and you have compute nodes with no internal network — processing capacity that data cannot reach fast enough to be useful.
💡 HBM (High Bandwidth Memory) stacks multiple memory dies vertically to deliver far higher data transfer rates than conventional DRAM. HBM architecture and why it needs CoWoS to ship goes into the detail — this article is focused on the CoWoS integration step itself.
Why Is CoWoS the Real Bottleneck — Not the Silicon Itself?
Wafer fabrication and CoWoS packaging are two independent manufacturing constraints. Fixing one does not fix the other. A fabricated wafer is not a shippable product — it still has to go through CoWoS integration before it becomes an AI accelerator. So all those headlines about new fabs and expanded wafer output? They do not translate into more GPUs until CoWoS capacity grows to match.
Epoch AI‘s analysis puts some numbers on this: the four largest AI chip designers — Nvidia, Google, AMD, and Amazon — collectively consumed over 90% of global CoWoS capacity and HBM supply by value in 2025, but only about 12% of global advanced logic die production. Packaging was the bottleneck. Not wafers.
CoWoS capacity has grown fast. Roughly 13,000–16,000 WPM at end-2023. Then 35,000–40,000 WPM at end-2024. Then 65,000–75,000 WPM at end-2025. Growing — but demand grows right alongside it, keeping everything fully allocated at every point along the way.
💡 WPM (wafers per month) is the standard capacity unit you will see in CoWoS reporting. When you see headlines about TSMC packaging capacity, this is the number to track.
The process is also qualitatively different from standard back-end assembly. CoWoS requires cleanrooms, silicon interposer fabrication, TSV drilling, and RDL formation — capabilities that are tightly coupled with front-end process technology.
💡 TSV (through-silicon via) is a vertical electrical connection drilled through a silicon die — a micro-fabrication step requiring near-front-end cleanroom precision. RDL (redistribution layer) is a metal wiring layer that reroutes electrical connections as part of the CoWoS integration stack.
Nvidia has confirmed it directly: “CoWoS assembly capacity is oversubscribed through at least mid-2026.” This structural shortage has separate capital requirements and expansion timelines from wafer fabrication. It is its own problem.
Why Can’t TSMC Just Build More CoWoS Capacity Faster?
Three reasons: capital intensity, specialised equipment lead times, and a process-packaging integration that only TSMC masters at AI-chip scale. The silicon interposer fabrication step requires front-end cleanroom standards — this is not standard back-end assembly. TSMC is expanding toward 120,000–130,000 WPM by end-2026, but demand is growing at the same pace.
The equipment queue is the first problem. CoWoS expansion needs ASML lithography tools and Applied Materials deposition equipment — the same supply-constrained tools used in front-end logic fabrication, with 12–18 month lead times. You cannot shortcut the queue.
The process integration lock is the second. CoWoS is tightly coupled to TSMC’s N3/N5 front-end process. The interposer geometry, bump pitch, and thermal management stack are all calibrated to the specific logic node. Handing the packaging step to a third party means requalifying the entire chip-packaging pipeline — years, not months.
💡 OSAT (Outsourced Semiconductor Assembly and Test) is the traditional back-end packaging industry — companies like ASE Group, Amkor, and Powertech. They handle less demanding integration steps but lack TSMC’s silicon interposer fabrication capability.
Can ASE Group or Amkor substitute? Partially, on a 2027/2028 horizon, and not at Nvidia-class volumes. What they cannot replicate is silicon interposer fabrication plus process-node coupling. Intel’s EMIB and Foveros represent real capability but do not match TSMC CoWoS at the scale required for current Nvidia and AMD production. And cost-wise, a single CoWoS wafer carries an average selling price of approximately US$10,000 — approaching the cost of a 7nm logic wafer. This is not cheap back-end assembly.
Nvidia Holds 60% of CoWoS Capacity — What Does That Mean for Everyone Else?
Even as TSMC expands CoWoS capacity, the allocation of that capacity is itself a binding constraint — and one company holds the majority of it.
Nvidia holds approximately 60–63% of TSMC’s total CoWoS capacity. Even as TSMC expands output, the majority of new capacity flows to Nvidia’s Blackwell backlog and Vera Rubin ramp. AMD’s MI300X and MI350, Google’s TPUs, and Amazon’s Trainium products are all competing for the remaining 37–40%.
The practical result: Blackwell delivery windows have slipped into Q1 2027. Lead times run 36 to 52 weeks. This is a packaging allocation problem, not an inventory problem.
What about AMD MI300X? Choosing AMD does not bypass the CoWoS constraint. AMD is the second-largest consumer of TSMC CoWoS capacity — MI300X and MI350 both require HBM3E and CoWoS packaging. AMD availability may be somewhat better in specific quarters precisely because Nvidia holds a larger share, but you are still in the same queue. Just a different line.
The forward trajectory makes this worse. Nvidia’s Vera Rubin requires HBM4 and more demanding CoWoS integration than Blackwell — eight stacks of HBM4, 288GB capacity, 22 TB/s bandwidth. Packaging requirements grow with each GPU generation. New capacity released by Blackwell completion will be consumed by Vera Rubin ramp.
For context on how Samsung is responding to TSMC’s packaging dominance, see the Samsung alternative packaging exploration piece.
TSMC Arizona: Policy Intent vs. Operational Reality
TSMC is building fabs in Arizona with a $165 billion total investment pledge. But CoWoS packaging capability at that site is not targeted until 2029. Right now, wafers fabricated at TSMC Arizona are shipped back to Taiwan for CoWoS packaging. Amkor Technology is building an Arizona packaging facility targeting early 2028, but it cannot substitute for TSMC CoWoS at current AI-chip volumes.
TSMC deputy COO Kevin Zhang confirmed the timeline: CoWoS and 3D-IC packaging capabilities at Arizona are targeted “before 2029.” The operational reality is that TSMC Arizona produces wafers. Those wafers cross the Pacific to Taiwan for CoWoS integration. They come back as finished GPUs. The supply chain still depends on Taiwan for the step that is the actual binding constraint.
This is the most important data point for any CTO building AI infrastructure plans. “America is making chips” is accurate. It is also incomplete. The packaging gap is a 2029 problem, not a solved one.
The CHIPS Act subsidises domestic semiconductor manufacturing — largely for wafer fabrication. It does not contain a specific packaging provision that closes the 2029 gap. The Amkor Arizona development is a real contribution to US packaging resilience, but it is not TSMC CoWoS-class silicon interposer integration at Nvidia volumes.
For the US supply chain implications, see Micron’s US memory strategy and its CoWoS dependency.
CoPoS Panel-Level Packaging: The Next Step Forward — and Why 2028–2029 Is Not Soon Enough
CoPoS — Chip-on-Panel-on-Substrate — is TSMC’s next-generation packaging technology. It uses larger rectangular panels instead of round wafers, which enables higher throughput and lower cost per unit. TSMC’s CoPoS pilot line at Chiayi is targeting June 2026 completion; volume production ramp is not expected until 2028–2029. CoPoS is the first genuine structural relief valve for the CoWoS bottleneck — but it will not arrive within the typical 18-month enterprise planning cycle.
CoPoS addresses a geometry problem. As AI chip packages grow larger — Nvidia’s Rubin GPU reaches 5.5x reticle size, meaning a standard 12-inch round wafer can accommodate as few as 4 units — round wafer-based production becomes increasingly inefficient. Panel-level packaging uses rectangular panels with more units per run and lower cost per unit.
Here is how the two technologies compare. CoWoS uses round 12-inch silicon wafers with silicon interposer fabrication, is fully allocated today, and is in volume production now. CoPoS uses rectangular glass or organic panels, replaces the silicon interposer with a glass substrate in advanced versions, and offers higher throughput — but is currently pilot only, with volume production expected 2028–2029.
Tool deliveries to TSMC’s CoPoS R&D teams began in February 2026, with full pilot line completion at Chiayi targeting June 2026. Warpage control during thermal processing is the key technical hurdle. The 2028–2029 timeline is an expectation, not a guarantee. Decisions made in 2026 cannot assume CoPoS availability.
Samsung is also exploring alternative packaging approaches — see the Samsung alternative packaging and competitive recovery article for the full picture. For a broader view of how the CoWoS bottleneck sits within the wider AI memory crunch, the series overview maps every layer of the shortage from HBM fabrication through to enterprise procurement.
What Does CoWoS Scarcity Mean for Enterprise GPU Availability in 2026 and 2027?
Enterprise buyers face Blackwell delivery slippage to Q1 2027 because CoWoS allocation — not wafer supply — is the binding constraint. Choosing AMD MI300X does not avoid this. For organisations that cannot secure on-premise GPU allocations, cloud GPU reservations are the practical alternative while CoWoS constraints persist through 2026 and into 2027.
Data centre GPUs carry 36 to 52 week lead times. Organisations that plan GPU requirements 18–24 months ahead are simply better positioned than those relying on spot procurement. That is not a complicated insight, but it is the one that matters right now.
CoWoS expansion is happening — the 65K to 120K+ WPM growth by end-2026 is a near-doubling of capacity. But demand grows in parallel. The Big Five hyperscalers committed a combined $600–630 billion in capex for 2026, with roughly 75% targeting AI infrastructure. Their purchasing power secures CoWoS capacity ahead of enterprise buyers. The constraint is easing slowly, not resolving.
For enterprises that cannot secure on-premise Blackwell allocations, cloud GPU reservations — AWS, Azure, GCP — are the near-term practical path. Not a packaging-free option. You are renting access to constrained hardware that hyperscalers queued for first. For on-premise or multi-cloud portability requirements, Nvidia remains the primary accelerator strategy for the next 18 months — and procurement timelines need to reflect that.
The planning summary: CoPoS volume relief is 2028–2029. OSAT alternatives are approaching CoWoS-class capability on a 2027/2028 horizon but at lower volumes. Assume CoWoS constraints persist for the full 2026 planning cycle and plan accordingly.
FAQ
Why can’t Intel or Samsung do CoWoS packaging instead of TSMC?
The barrier is not just equipment — it is the tight coupling between TSMC’s N3/N5 front-end process and the CoWoS packaging step. Replicating that at a different foundry means requalifying the entire chip-packaging pipeline. Years, not months. TSMC leads on both bottlenecks simultaneously — process and packaging — and catching up on one while the other remains behind does not solve the problem.
Intel has EMIB and Foveros technologies, but neither matches TSMC CoWoS at the volume required for current Nvidia and AMD production. Samsung is exploring alternatives (covered in the Samsung packaging piece) but is not a near-term substitute at Nvidia-class volumes.
Does buying AMD MI300X avoid the CoWoS constraint?
No. AMD MI300X and MI350 require HBM3E and TSMC CoWoS packaging — the same infrastructure as Nvidia Blackwell. AMD is the second-largest consumer of TSMC CoWoS capacity. Choosing AMD shifts which CoWoS queue you depend on, not whether you depend on CoWoS. From a hardware availability standpoint, AMD does not bypass the packaging bottleneck.
Will TSMC’s Arizona expansion solve the packaging shortage for US buyers?
No. Chips fabricated at TSMC Arizona today are shipped back to Taiwan for CoWoS packaging. CoWoS capability at Arizona is confirmed as targeting “before 2029” by TSMC deputy COO Kevin Zhang. Amkor’s Arizona facility targets early 2028 — a partial contribution to US supply chain resilience, but not a substitute for TSMC CoWoS at AI-chip scale.
What is a silicon interposer and why does it matter?
A silicon interposer is a thin silicon die that sits between the GPU logic die and the substrate, acting as a high-density wiring layer connecting the GPU and HBM stacks via thousands of short electrical paths. It enables connection densities that conventional PCB substrates cannot achieve — AI accelerators need this density for transformer model inference and training.
Fabricating silicon interposers at the required density is itself a near-front-end precision process. This is why OSAT companies cannot replicate CoWoS: they do not operate front-end-class cleanrooms.
What is CoPoS and when will it relieve CoWoS pressure?
CoPoS uses larger rectangular panels instead of round silicon wafers, enabling more units per run and lower cost per unit. TSMC’s CoPoS pilot line at Chiayi began tool deliveries in February 2026, with full pilot line completion targeted for June 2026. Volume production ramp is expected in 2028–2029. CoPoS does not relieve CoWoS pressure before 2028 at the earliest. Do not factor it into 2026–2027 supply chain assumptions.
Why is Nvidia Blackwell so hard to get in 2026?
Nvidia holds approximately 60–63% of TSMC’s total CoWoS capacity. Even as TSMC expands output toward 120,000–130,000 WPM by end-2026, the majority flows to Nvidia’s Blackwell backlog and Vera Rubin ramp. Blackwell delivery windows have slipped to Q1 2027 with lead times of 36 to 52 weeks. The cause is packaging allocation, not silicon production.
What is OSAT and why can’t OSAT companies replace TSMC for CoWoS?
OSAT — Outsourced Semiconductor Assembly and Test — is the traditional back-end packaging and testing industry: ASE Group, Amkor, Powertech, and others. OSAT companies cannot replicate CoWoS because it requires silicon interposer fabrication (a near-front-end process) and tight integration with TSMC’s specific logic process nodes. ASE Group and Amkor are approaching CoWoS-class capability on a 2027/2028 horizon — at lower volumes and without the silicon interposer fabrication step.
How much does CoWoS packaging cost and how does it affect chip economics?
A single CoWoS wafer carries an average selling price of approximately US$10,000, approaching the cost of a 7nm advanced logic wafer. CoWoS carries a value-added rate approaching 50%, compared to 15–25% for traditional electronics manufacturing. There is no packaging-cost shortcut available from alternative providers at comparable capability.
Is cloud GPU capacity affected by CoWoS constraints?
Yes — hyperscaler GPU clusters are built from the same CoWoS-packaged GPUs as on-premise hardware. But hyperscalers have long-term allocation agreements that let them secure capacity ahead of enterprise buyers. If you cannot secure on-premise Blackwell allocations, cloud reservations are the near-term practical alternative — not a packaging-free option, but renting access to constrained hardware that hyperscalers secured first.
What happens to CoWoS demand when Nvidia launches Vera Rubin?
Vera Rubin requires HBM4 and more demanding CoWoS integration than Blackwell — eight stacks of HBM4 per package, 288GB capacity, 22 TB/s bandwidth. Packaging requirements grow with each GPU generation. New capacity released by Blackwell completion will be consumed by Vera Rubin ramp. The CoWoS bottleneck is structural, not cyclical.
